Smc-networks ARM PL241 Manual de usuario descargar pdf (Pagina 53)

Functional Overview

Figure 2-19 shows a burst read with the smc_wait_0 output of the memory used to

delay the transfer.

Note

• Synchronous memories have a configuration register enabling smc_wait_0 to be

asserted either on the same clock cycle as the delayed data or a cycle earlier. The

SMC only supports smc_wait_0 being asserted one cycle early, enabling

smc_wait_0 to be initially sampled with the fed back clock and then with

smc_mclk0 before being used by the FSM. This enables the easiest timing

closure. Additionally, you must configure the memory for smc_wait_0 to be

active LOW.

• In synchronous operation, the SMC relies on the smc_wait_0 signal being

deasserted HIGH to indicate that the memory can finish the transfer. When in

synchronous mode some memories do not deassert the smc_wait_0 signal during

non-array read transfers. Non-array read transfers are typically status register

reads. To avoid stalling the system with these memories, in synchronous mode

you must not perform non-array read transfers with the memory and SMC.

Figure 2-19 Synchronous burst read

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Smc-networks ARM PL241 Manual de usuario Pagina 53