Smc-networks ARM PL241 Manual de usuario

Copyright © 2006 ARM Limited. All rights reserved.ARM DDI 0389BPrimeCell® AHB SRAM/NORMemory Controller (PL241)Revision: r0p1Technical Reference Manua

Preface x Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BAbout this manualThis is the Technical Reference Manual (TRM) for the PrimeC

Signal Descriptions A-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BA.5 SMC miscellaneous signalsTable A-4 lists the SMC miscellan

Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-7A.6 Low-power interfaceTable A-5 lists the low-power interface

Signal Descriptions A-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BA.7 Configuration signalTable A-6 lists the configuration sign

Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-9A.8 Scan chainsTable A-7 lists the scan chain signals.Table A-

Signal Descriptions A-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-1GlossaryThis glossary describes some of the terms used in technical documen

Glossary Glossary-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BAdvanced Peripheral Bus (APB)A simpler bus protocol than AHB. It i

Glossary ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-3Boundary scan chainA boundary scan chain is made up of serially-co

Glossary Glossary-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BSBO See Should Be One.SBZ See Should Be Zero.SBZP See Should Be Ze

Glossary ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. Glossary-5Remapping Changing the address of physical memory or devices afte

Preface ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xiAppendix A Signal Descriptions Read this appendix for a description of the

Glossary Glossary-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B

Preface xii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BNote Angle brackets can also enclose a permitted range of values. The exa

Preface ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. xiiiPrefix B Denotes AXI write response channel signals.Prefix C Denotes AX

Preface xiv Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BFeedbackARM Limited welcomes feedback on the AHB MC and its documentation.

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-1Chapter 1 IntroductionThis chapter introduces the AHB MC. It contains the followin

Introduction 1-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B1.1 About the AHB MCThe AHB MC is an Advanced Microcontroller Bus Arc

Introduction ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-31.1.1 AHB interfaceThe interface converts the incoming AHB transfers

Introduction 1-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B1.1.3 SMC The SMC is a high-performance, area-optimized SRAM memory c

Introduction ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 1-51.2 Supported devicesThe SMC supports SRAM/NOR, see SMC on page 1-4.

ii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BPrimeCell AHB SRAM/NOR Memory Controller (PL241)Technical Reference ManualCopyrigh

Introduction 1-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-1Chapter 2 Functional OverviewThis chapter describes the major components of the AH

Functional Overview 2-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B2.1 Functional descriptionFigure 2-1 shows an AHB MC (PL241) c

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-32.1.3 Clock domainsThe memory controller has two clock domains

Functional Overview 2-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B2.2 SMCFigure 2-3 shows a block diagram of the SMC.Figure 2-3

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-52.2.1 SMC interfaceThe SMC interface processes the incoming AH

Functional Overview 2-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B2.2.6 Pad interfaceThe pad interface module provides a registe

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-72.3 Functional operationThis section is divided into:• AHB int

Functional Overview 2-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BUndefined length INCR burstsAll undefined length INCR bursts a

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-9If transfers are described as non-bufferable then the bridge m

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. iiiContentsPrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manua

Functional Overview 2-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BRegistered HWDATA The interconnect used within the AHB MC con

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-11Figure 2-6 AHBC memory mapThe other fourteen 4KB regions are

Functional Overview 2-12 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BStatic memory clocking optionsTable 2-1 lists the static memo

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-13an active output <domain>_cactiveWhere:<domain> i

Functional Overview 2-14 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BThe AHB domain accepts or denies requests based on whether it

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-152.4 SMC functional operationThis section describes:• Operatin

Functional Overview 2-16 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BThe state transitions are:Ready to Reset When reset is assert

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-17These clocks can be grouped into two clock domains:AHB domain

Functional Overview 2-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BYou can change both reset signals asynchronously to their res

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-19smc_msync0 When HIGH, indicates smc_mclk0 is synchronous to s

Contentsiv Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BChapter 4 Programmer’s Model for Test4.1 SMC integration test registers ..

Functional Overview 2-20 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BThe SMC ensures the ordering of read transfers from a single

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-21memory bursts, terminating a memory transfer at the burst bou

Functional Overview 2-22 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B2.4.6 Memory manager operationThe memory manager module is re

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-23The APB registers smc_set_cycles and smc_set_opmode act as ho

Functional Overview 2-24 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BDirect commandsThe SMC enables code to be executed from the m

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-25Figure 2-12 Device pin mechanism:ULWHWLPLQJSDUDPHWHUVDQGR

Functional Overview 2-26 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BFigure 2-13 Software mechanism:ULWHWLPLQJSDUDPHWHUVDQGRSH

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-272.4.7 Interrupts operationThe next read to any chip select on

Functional Overview 2-28 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BRead data output by the memory device is also registered on t

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-29Figure 2-14 Asynchronous readAsynchronous read in multiplexed

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. vList of TablesPrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference M

Functional Overview 2-30 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BNote In multiplexed-mode, both address and data are output by

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-31Asynchronous write in multiplexed-modeTable 2-8 and Table 2-9

Functional Overview 2-32 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BFigure 2-18 shows a page read access, with an initial access

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-33Figure 2-19 shows a burst read with the smc_wait_0 output of

Functional Overview 2-34 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BSynchronous burst read in multiplexed-modeTable 2-14 and Tabl

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-35Synchronous burst writeTable 2-16 and Table 2-17 list the smc

Functional Overview 2-36 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BSynchronous burst write in multiplexed-modeTable 2-18 and Tab

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-37Synchronous read and asynchronous writeTable 2-20 and Table 2

Functional Overview 2-38 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BFigure 2-23 Synchronous read and asynchronous writeProgrammin

Functional Overview ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-39For tWC:• when using memory devices that are not wait-enabled

List of Tablesvi Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BTable 2-21 Synchronous read and asynchronous write opmode chip regist

Functional Overview 2-40 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-1Chapter 3 Programmer’s ModelThis chapter describes the registers of the SMC and pr

Programmer’s Model 3-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B3.1 About the programmer’s modelThe SMC has 4KB of memory alloc

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-33.2 Register summaryFigure 3-2 shows the SMC configuration regi

Programmer’s Model 3-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BNote Figure 3-3 on page 3-3 shows the maximum number of support

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-5smc_set_cycles0x1014WO N/A See SMC Set Cycles Register at 0x101

Programmer’s Model 3-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B3.3 Register descriptionsThis section describes the SMC registe

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-73.3.2 SMC Memory Interface Configuration Register at 0x1004The

Programmer’s Model 3-8 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B3.3.3 SMC Set Configuration Register at 0x1008The write-only sm

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-9Table 3-4 lists the register bit assignments.3.3.4 SMC Clear Co

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. viiList of FiguresPrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Referenc

Programmer’s Model 3-10 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B3.3.5 SMC Direct Command Register at 0x1010The write-only smc_

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-113.3.6 SMC Set Cycles Register at 0x1014This is the holding reg

Programmer’s Model 3-12 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B3.3.7 SMC Set Opmode Register at 0x1018This register is the ho

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-13Table 3-8 lists the register bit assignments.Table 3-8 smc_set

Programmer’s Model 3-14 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B[9:7] set_wr_bl Holding register for value to be written to th

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-153.3.8 SMC Refresh Period 0 Register at 0x1020The read/write sm

Programmer’s Model 3-16 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BTable 3-10 lists the register bit assignments.3.3.10 SMC Opmod

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-17Table 3-11 lists the register bit assignments.Table 3-11 smc_o

Programmer’s Model 3-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B3.3.11 SMC User Status Register at 0x1200The smc_user_status R

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-193.3.12 SMC User Configuration Register at 0x1204The smc_user_c

List of Figuresviii Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BFigure 2-20 Synchronous burst read in multiplexed-mode ...

Programmer’s Model 3-20 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BFigure 3-18 shows the correspondence between bits of the smc_

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-21SMC Peripheral Identification Register 1The smc_periph_id_1 Re

Programmer’s Model 3-22 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B3.3.14 SMC PrimeCell Identification Registers <0-3> at 0

Programmer’s Model ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 3-23The following sections describe the smc_pcell_id Registers:• S

Programmer’s Model 3-24 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BSMC PrimeCell Identification Register 2The smc_pcell_id_2 Regi

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 4-1Chapter 4 Programmer’s Model for TestThis chapter describes the additional logic f

Programmer’s Model for Test 4-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B4.1 SMC integration test registersTest registers are p

Programmer’s Model for Test ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 4-3Table 4-2 lists the register bit assignments.4.1.2 Int

Programmer’s Model for Test 4-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B4.1.3 Integration Outputs Register at 0x1E08The write-

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-1Chapter 5 Device Driver RequirementsThis chapter contains various flow diagrams to

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. ixPrefaceThis preface introduces the PrimeCell AHB SRAM/NOR Memory Controller (MC) (P

Device Driver Requirements 5-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B5.1 Memory initializationFigure 5-1 on page 5-3 and Fig

Device Driver Requirements ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-3Figure 5-1 SMC and memory initialization sheet 1 of 36W

Device Driver Requirements 5-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BFigure 5-2 SMC and memory initialization sheet 2 of 36K

Device Driver Requirements ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 5-5Figure 5-3 SMC and memory initialization sheet 3 of 3Wh

Device Driver Requirements 5-6 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-1Appendix A Signal DescriptionsThis appendix lists and describes the processor sign

Signal Descriptions A-2 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BA.1 About the signals listThis appendix lists the PL241 signal

Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-3A.2 Clocks and resetsTable A-1 lists the clock and reset signa

Signal Descriptions A-4 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389BA.3 AHB signals Table A-2 lists the AHB signals.where:<x>

Signal Descriptions ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. A-5A.4 SMC memory interface signalsTable A-3 lists the SMC memory